5.6.4 shows how the propagation delays created by the gates in each flip-flop (indicated by the blue vertical lines) add, over a number of flip-flops, to form a significant amount of delay between the time at which the output changes at the first flip flop (the least significant bit), and the last flip flop (the most significant bit).Īs the Q 0 to Q 3 outputs each change at different times, a number of different output states occur as any particular clock pulse causes a new value to appear at the outputs.Īt CK pulse 8 for example, the outputs Q 0 to Q 3 should change from 1110 2 (7 10) to 0001 2 (8 10), however what really happens (reading the vertical columns of 1s and 0s in Fig. 5.6.4, which is a magnified section (pulse 8) of Fig. The effect of clock ripple in asynchronous counters is illustrated in Fig. As this is a four-stage counter the flip-flops will continue to toggle in sequence and the four Q outputs will output a sequence of binary values from 0000 2 to 1111 2 (0 to 15 10) before the output returns to 0000 2 and begins to count up again as illustrated by the waveforms in Fig 5.6.2.įig.5.6.4 Timing Diagram Detail Showing Clock Ripple Clock Ripple
Reading the output word from right to left, the Q outputs therefore continue to represent a binary number equalling the number of input pulses received at the CK input of FF0.
The fourth CK pulse will make both Q 0 and Q 1 return to 0 and as Q 1 will go high at this time, this will toggle FF2, making Q 2 high and indicating 0010 2 (4 10) at the outputs. The next (third) CK pulse will cause Q 0 to go to logic 1 again, so both Q 0 and Q 1 will now be high, making the 4-bit output 1100 2 (3 10 remembering that Q 0 is the least significant bit). The Q outputs then represent a four-bit binary count with Q 0 to Q 3 representing 2 0 (1) to 2 3 (8) respectively.Īssuming that the four Q outputs are initially at 0000, the rising edge of the first CK pulse applied will cause the output Q 0 to go to logic 1, and the next CK pulse will make Q 0 output return to logic 0, and at the same time Q 0 will go from 0 to 1.Īs Q 0 (and the CK input of FF1 goes high) this will now make Q 1 high, indicating a value of 2 1 (2 10) on the Q outputs. The rising edge of the Q output of each flip-flop triggers the CK input of the next flip-flop at half the frequency of the CK pulses applied to its input.
Clock pulses are fed into the CK input of FF0 whose output, Q 0 provides the 2 0 output for FF1 after one CK pulse. 5.6.1 shows a 4 bit asynchronous up counter built from four positive edge triggered D type flip-flops connected in toggle mode. They are normally shown in schematic diagrams in reverse order, with the least significant bit at the left, this is to enable the schematic diagram to show the circuit following the convention that signals flow from left to right, therefore in this case the CK input is at the left. The output lines of a 4-bit counter represent the values 2 0, 2 1, 2 2 and 2 3, or 1,2,4 and 8 respectively.
#DIGITAL WORKS DISPLAY A NUMBER SERIES#
The output is a binary value whose value is equal to the number of pulses received at the CK input.Įach output represents one bit of the output word, which, in 74 series counter ICs is usually 4 bits long, and the size of the output word depends on the number of flip-flops that make up the counter. Counters, consisting of a number of flip-flops, count a stream of pulses applied to the counter’s CK input.
0 kommentar(er)
